fifo.vhd

fifo.vhd

fifo.vhd is an implementation of a fifo queue

    fifo
generic integer bits
the queue will have a capacity of 2^bits elements of 8 bits
in std_logic clk
clock for the communication with the module
in

std_logic

rst
signal to reset the fifo (empty queue)
in std_logic wr
If '1', push the data from write to the queue
in std_logic [8] write
vector of data to write to the queue if wr is '1'
out std_logic [8] read
vector where data is stored from the queue if rd is '1'
out std_logic full
flag set when the queue is full
out std_logic empty
flag set when the queue is empty


How to use :
You need to provide a clock signal to the input clk, the read or write operations will be applied at rising edge of clk

To change the capacity of the queue :
Just change the generic value bits to change the capacity, the capacity is 2^bits bytes

How to write (push) a byte to the fifo :
Put the data you want to write in the write vector and set wr to '1'.
If the queue is not full, the data will be pushed at rising edge of clk.

How to read (pop) a byte from the fifo :
Set rd to '1', if the queue is not empty, the data will be popped at rising edge of clk to read.

 

 

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Date de dernière mise à jour : 12/06/2015

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