fifo.vhd is an implementation of a fifo queue
the queue will have a capacity of 2^bits elements of 8 bits
clock for the communication with the module
signal to reset the fifo (empty queue)
If '1', push the data from write to the queue
vector of data to write to the queue if wr is '1'
vector where data is stored from the queue if rd is '1'
flag set when the queue is full
flag set when the queue is empty
How to use :
You need to provide a clock signal to the input clk, the read or write operations will be applied at rising edge of clk
To change the capacity of the queue :
Just change the generic value bits to change the capacity, the capacity is 2^bits bytes
How to write (push) a byte to the fifo :
Put the data you want to write in the write vector and set wr to '1'.
If the queue is not full, the data will be pushed at rising edge of clk.
How to read (pop) a byte from the fifo :
Set rd to '1', if the queue is not empty, the data will be popped at rising edge of clk to read.
Date de dernière mise à jour : 12/06/2015