uart_brgen implements a baudrate generator for the uart module.

in std_logic clk
source clock


signal to reset
in std_logic en
If '1', the module is enabled
in std_logic [16] count
initial value of the counter, clkout frequency divided by (count+1)
out std_logic clkout
output clock signal, frequency is equal to clk frequency divided by (count+1)

How it works :
A counter signal is initialised to count and decrement by 1 at each rising edge of clk.
When the counter is equal to 0, the clkout signal is set to '1' and the counter is reset to count.
This provides a signal clkout whose frequency is the frequency of clk divided by (count+1).

How to pause the module :
If you set en to '0', the module will be paused (the counter doesn't decrement anymore), the clkout signal is set to '0'.
When en is set to '1' again, this resume where it was stopped.


Date de dernière mise à jour : 12/06/2015