zpuino_uart_mv_filter implements a majority voting filter

generic natural bits
size (in bits) of the counter, the range is 0...2^bits-1
generic natural threshold
number of vote needed to set sout to '1'
in std_logic clk
source clock


signal to reset
in std_logic sin
input signal, at each rising edge of clk, a vote is counted if sin equal to '1'
out std_logic sout
output signal, equal to '1' if the number of votes is greather or equal to threshold, otherwise equal to '0'
in std_logic clear
reset the vote count to 0
in std_logic enable
If '1', the module is enabled

How it works :
A vote counter signal is initialised to 0. At each rising edge of clk, if the sin signal is equal to '1', it increments the counter.
If the counter is above threshold, the output signal is equal to '1', otherwise equal to '0'.

How to reset the vote counter :
Either set rst to '1', or clear to '1', the effect is the same.

How to pause the module :
If you set enable to '0', the module will be paused (doesn't increment the vote counter when sin is equal to '1'), the sout signal keep its value.
It's still possible to clear or reset the counter.


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Date de dernière mise à jour : 12/06/2015