zpuino_uart_rx implements the receiver unit for uart
signal to reset
input data signal (data from the uart emitter)
input clock (clock from the uart emitter)
signal to read data (the only effect is to reset data_av when data is not available, the data will be read normally even if read is not '1')
vector of the received data (complete only when data_av is '1')
flag set when data is available (Note : read needs to be set to '1' otherwise data_av is not reset when data is not available)
How it works :
A baud is generated by a uart_brgen module, the frequency is 1/16 of clk.
The signal rx is oversampled and a majority vote zpuino_uart_mv_filter (with threshold : votes >= 10/16) is used, I assume this reduce the risk of error due to noise on the transmission.
The transmission begins when rx (oversampled) is set to '0' during a baud tick, then 8 bits are read from rx (oversampled) at each baud tick and stored in data.
After the 8 bits, if the rx (oversampled) is equals to '1' at the baud tick, the transmission is validated, data_av is set to '1'.
Date de dernière mise à jour : 13/06/2015